Document Type and Number:
Japanese Patent JPH0380369
Kind Code:
B2
Abstract:
A combined phase detector and low pass filter comprises charge storage means (10) which is responsive to an input signal (VI) and which is charged to a level dependent upon the magnitude and phase of the input signal in response to a first control signal (S1) which is a digital signal of given frequency. The potential stored in the charge storage means (10) is alternatively gated out by first and second gating circuits (12,14) into an integrating circuit (16) having an output VO. The gating circuits are connected such that the polarity of the connection of the stored potential to the integrating circuit is alternated. The gating circuits are responsive to second and third control signals (S2, S3), respectively, the second and third control signals having a frequency one-half that of the first control signal, and the phase difference between the second and third control signals being 180 degrees. The rate of increase in magnitude of the output signal (VO) represents the phase difference between the input signal and the first control signal.
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Inventors:
GEI MAIKERU JON
Application Number:
JP50087283A
Publication Date:
December 24, 1991
Filing Date:
January 31, 1983
Export Citation:
Assignee:
MOTOROLA INC
International Classes:
H03D3/22; H03D1/22; H03D13/00; H03H11/04; H03H19/00