PURPOSE: To decrease the synchronization return time by a time of forward protection till out of frame synchronization takes place by providing a shift register circuit bringing a frame synchronization circuit into out of synchronism state when a clock phase is inverted to the multiplexer/demultiplexer.

CONSTITUTION: A shift register circuit 8 is provided, which detects a clock phase inverting pulse of a block synchronization circuit 3 to delay a clock phase inverting pulse and inputting the delayed pulse to a frame synchronization circuit 6 so as to output a frame synchronization reset signal to bring the frame synchronization circuit 6 into out of synchronism state in a proper timing to the frame synchronization circuit 6. Thus, when block synchronization is unlocked and the phase of the clock is inverted, frame synchronization is immediately unlocked to implement synchronization locking and then the synchronization restoration time till the frame synchronization is locked and a correct data is outputted is reduced.