Document Type and Number:
Japanese Patent JPH0467811
Kind Code:
B2
Abstract:
A programmable delay generator is based upon an asynchronous or ripple counter (10) the stages (11,12,13,14) of which change state at definably different times. A full terminal count is decoded (18) including the condition of a lowest order stage (16) which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.
Inventors:
JOOJI JEI KASUPERU
AGOSUTON AGOSUTON
AGOSUTON AGOSUTON
Application Number:
JP7296087A
Publication Date:
October 29, 1992
Filing Date:
March 26, 1987
Export Citation:
Assignee:
TEKTRONIX INC
International Classes:
H03K5/135; H03K23/66
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