Document Type and Number:
Japanese Patent JPH0473889
Kind Code:
B2
Abstract:
PURPOSE:To generate a pulse with a duty factor of around 50% with a minimum number of shifting stages, by providing a gate means which pulls in the pulse of each stage of a prescribed shift means and generates a prescribed pulse by applying a logical operation on the pulse. CONSTITUTION:The output pulses (a) and (b) of a NOR20a which pulls in the detecting pulse of each stage of FFs 10a-10d consisting of a shift register of four stages, and a NOR20b which pulls in the detecting pulse of each stage of FFs 10a-10c are validated alternately by the output condition of an FF30a. And the signal is inputted to the data terminal D of the FF10a via an OR20c, and is shifted in order by an inputting clock CLK. next, the output condition of the FF30a is added, and the output pulse (a) of the NOR20a is validated at the 5th bit of the clock CLK, and hereafter, the above operation is repeated.
More Like This:
Application Number:
JP11980487A
Publication Date:
November 24, 1992
Filing Date:
May 15, 1987
Export Citation:
International Classes:
H03K3/017; H03K3/78; H03K5/00; H03K23/54; H03K23/64; H03K23/66
Next Patent: JPH0473890