Document Type and Number:
Japanese Patent JPH0474898
Kind Code:
B2
Abstract:
PCT No. PCT/JP83/00093 Sec. 371 Date Nov. 29, 1983 Sec. 102(e) Date Nov. 29, 1983 PCT Filed Mar. 28, 1983 PCT Pub. No. WO83/03502 PCT Pub. Date Oct. 13, 1983.When the frequency dividing ratio of a programmable divider in a phase locked loop is controlled by an up/down counter, the designing of a system can be simplified by reducing the number of control lines connected to a microprocessor as much as possible. An up/down counter control circuit of the present invention comprises a timing control means to which a latch signal, a data and a clock signal are supplied, a data memory means and an up/down counter and is characterized in that under the control of the timing control means, in the data latch mode, a first level (0 or 1) of the latch signal is detected and in synchronism with the clock signal that data is latched in the data memory means, while in the up/down mode, a second level (1 or 0) of the latch signal is detected and the content of the up/down counter is changed in response to the level of the data synchronized with the clock signal.
Application Number:
JP5446582A
Publication Date:
November 27, 1992
Filing Date:
April 01, 1982
Export Citation:
International Classes:
H03L7/18; H03J5/02; H03J7/28; H03K21/02; H03K23/66; H03K23/86; H03L7/183; H04B1/26
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