Document Type and Number:
Japanese Patent JPH0510108
Kind Code:
B2
Abstract:
A digital circuit requiring minimum power for accurately and reliably measuring the average pulse rate of a periodic signal. The circuit includes a plurality of flip-flop stages adapted to be configured by control gates either as a binary counter or a shift register in response to the pulses of the periodic input signal. Through a series of configuration gates, each pulse momentarily configures the circuit as a shift register and effects a shift operation, e.g. a divide-by-two operation. After each pulse, the circuit resumes a counter configuration and counts the clock pulses of a crystal controlled clock oscillator. After a few input pulses, the contents of the counter immediately after each shift operation indicates the average periodic rate of the periodic signal in much the same manner as a conventional R-C network. However, the digital circuit is not suseptable to drift caused by temperature changes and also moderates the effects of momentary irregularities in the periodic rate of the signal. In application of the digital circuit, a digital comparator of an implanted cardiac cardioverter compares the counter contents with a preset value which, when exceeded, triggers a cardiac analyzing circuit which determines whether the automatic cardioverter is appropriate.
Inventors:
MIAA IMURAN
Application Number:
JP3255785A
Publication Date:
February 08, 1993
Filing Date:
February 20, 1985
Export Citation:
Assignee:
MIROWSKI MIECZYSLAW
International Classes:
A61N1/08; A61B5/0452; A61N1/365; A61N1/39; G01R23/02; G01R23/10; H03K23/50
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