Document Type and Number:
Japanese Patent JPH0528007
Kind Code:
B2
Abstract:
An integrated divide-by-two frequency divider circuit in BFL logic of the master-slave flip-flop type which comprises two complementary outputs Q and &upbar& Q and only a single input for a control signal. The divider is formed only by NOR gates and wired-OR gates. The master does not have a memory function and the various transistors are proportioned so that, tau 1 being the transit time in the master, tau 3 the transit time in the first and the second NOR-gate (G3 and G4) of the slave, and tau 4 the transit time in the fourth and the third NOR gate (G4 and G5) of the slave, the following inequality is satisfied tau 1=1( tau 3+ tau 4), thus resulting in a maximum operating frequency which is defined by the relation fmax=1/( tau 1+ tau 3+ tau 4). This circuit is integrated by means of depletion MESFET transistors on a gallium arsenide substrate in a technology including inverter-type gates which are followed by a level translator stage. The invention is used for processing of signals in the gigahertz frequency range of up to 5 GHz.
Inventors:
MAARU ROTSUSHII
Application Number:
JP13019484A
Publication Date:
April 23, 1993
Filing Date:
June 26, 1984
Export Citation:
Assignee:
FUIRITSUPUSU FURUUIRANPENFUABURIKEN NV
International Classes:
H03K3/037; H03K3/3562; H03K23/00; H03K23/50
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