Document Type and Number:
Japanese Patent JPH0530087
Kind Code:
B2
Abstract:
PURPOSE:To attain high speed output signal by constituting the output section by a bipolar transistor(TR) and giving an output signal with an opposite polarity to the input signal according to the 1st and 2nd clock signals and holding the output state. CONSTITUTION:An input section I consists of N-channel MOS TRs N1-N4, an inverter I11 and a resistor R1. An output section II consists of NPN bipolar TRs Q1, Q2 clamped by a Schottky barrier diode, an NPN bipolar TR Q3 not clamped, a resistor R2 and a pull-down circuit P.D. In applying the 1st and 2nd clock signals phi, the inverse of phi, the level inverted to the level of the input signal D before the clock signal is applied is given as the output signal and in stopping the application of the clock signal, the output stage is held regardless of the change in the input signal D. Thus, the high operating speed and high load drive capability are attained.
Inventors:
UENO SHOJI
Application Number:
JP24675187A
Publication Date:
May 07, 1993
Filing Date:
September 30, 1987
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03K3/356; H03K23/00; H03K23/40; H03K23/52
Next Patent: CLOCK PHASE ADJUSTING CIRCUIT