Title:
【発明の名称】オフセットを相殺した高速比較器
Document Type and Number:
Japanese Patent JPH05504871
Kind Code:
A
Abstract:
A regenerative latch includes a fully differential amplifier with two inputs and two outputs and two positive feedback paths, each path coupling each of the two outputs to one of the two inputs through a capacitor. Hence, during the reset phase, the two capacitors will block all DC voltages thereby enabling offset cancellation of the amplifier. During the regeneration phase, the two positive feedback paths drive the amplifier quickly into saturation. The output of the regenerative latch may be used to drive a second stage latch to reduce metastability and to reduce the gain requirements for the latch. The transistor channels of the input transistors of the second stage latch are reverse biased into depletion regions to reduce the input capacitance of the second latch during reset. Such low input capacitance speeds up the regeneration of the first stage latch.
Inventors:
Liu Edward Wy Young
Application Number:
JP51503390A
Publication Date:
July 22, 1993
Filing Date:
October 16, 1990
Export Citation:
Assignee:
VIS Technology Incorporated
International Classes:
H03K3/356; H03K5/08; (IPC1-7): H03K3/353; H03K5/26
Attorney, Agent or Firm:
Toshi Inoguchi