Document Type and Number:
Japanese Patent JPH0551185
Kind Code:
B2
Abstract:
A semiconductor memory device comprises an address line, a write line, a read line, and a memory cell connected to the address, write and read lines, where the memory cell comprises a power source, an RHET, a switching element and a data transfer element. The power source is coupled to a base of the RHET through a first resistor so that the RHET has a plurality of stable states. The switching element is coupled between the write line and the base of the RHET, and is controlled by a signal from the address line. The data transfer element is coupled between a collector of the RHET and the read line, and the collector is coupled to the power source through a second resistor. When reading an information from the memory cell, a signal corresponding to one of the plurality of stable states of the RHET is transmitted to the read line via the data transfer element.
Inventors:
MORI TOSHIHIKO
Application Number:
JP13863086A
Publication Date:
July 30, 1993
Filing Date:
June 14, 1986
Export Citation:
Assignee:
KOGYO GIJUTSUIN
International Classes:
G11C11/411; G11C11/34; G11C11/36; G11C11/39; G11C11/41; G11C11/56; H01L27/10; H01L29/201; H01L29/68; H03K3/357; H03K3/36; H03K23/00; (IPC1-7): H01L29/68; G11C11/41; H03K3/357
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