Document Type and Number:
Japanese Patent JPH0554138
Kind Code:
B2
Abstract:
An asynchronous FIFO (firstin, firstout) device suitable for use as a buffer comprises a stack having a plurality of sections. Each section has a data storage register and a control subassembly. Each assembly is associated with one of said data storage registers. A single data input is connected to the first data storage register. The data storage registers have a transparent condition and a latched condition and each subassembly comprises a 2-to-1 MUX (multiplexer) having a first input connected to receive a logic signal indicative of the condition of the preceding subassembly, a second input connected to receive a logic signal indicative of the condition of the following subassembly and an output connected to the associated storage register. The MUX is constructed to deliver on its output a signal representative of the condition of the subassembly and its internal connections are determined by the logic level of the output signal of the MUX.
Inventors:
ARAN TOMASU
MISHERU SERUERU
MISHERU SERUERU
Application Number:
JP20392184A
Publication Date:
August 11, 1993
Filing Date:
September 28, 1984
Export Citation:
Assignee:
ARAN TOMASU
MISHERU SERUERU
MISHERU SERUERU
International Classes:
G06F9/46; G06F5/08; G11C7/00; H03K23/66; (IPC1-7): G06F9/46; G11C7/00
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