Japanese Patent JPH0554287

B2

An endless counting apparatus comprises a first memory (9, 33) for storing a code of a first predetermined number of bits sufficient to represent the maximum value of each coded input expressed according to the binary notation, a second memory (9, 34, 35) for storing an endless-making code of a second predetermined number of bits of higher order than and contiguous to the less and least significant bits stored in the first memory, and a control circuit (9,32) for adding or subtracting the value of the coded input to or from the contents of the first and second memories depending on the input value to be counted and applying the result of addition or subtraction to the first and second memories. A method for endless counting by such an apparatus comprises clearing the most signficant bit of the endless making code stored in the second memory when the code stored in the second memory has attained a value which causes an overflow due to a carry from the contents of the first memory if the carry occurs, and setting the most significant bit of the endless-making code stored in the second memory when the code stored in the second memory has attained a value which causes an underflow due to a borrow from the contents of the first memory if the borrow occurs.

HAYASHIDA HIROSHI
MYASHITA KUNIO
TAKAHASHI TADASHI
MORINAGA SHIGEKI
ISHIZAKI KIMYOSHI

JP5959682A

August 12, 1993

April 12, 1982

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HITACHI LTD

G06K15/16; B41J11/42; G05B19/29; G06F3/12; H03K23/66; (IPC1-7): H03K23/66; B41J11/42; G06F3/12

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