【発明の名称】フューズ切換回路

Japanese Patent JPH06101234

B2

PURPOSE:To reduce the current consumption of a system by composing the title device of a first CMOS inverter, a second CMOS inverter including a fuse, and an MOS transistor for a feedback. CONSTITUTION:The device is composed of a first CMOS inverter 1, a second CMOS inverter 4 including a fuse 7, and an MOS transistor 8 of a third N channel, and for the input of the second CMOS inverter 4, an auto-clear pulse ACL, which is outputted at the time of impressing power source Vcc voltage, is given. In this case, the power source is impressed at the time of a fuse disconnection, and after a while, for a route from the power source Vcc to a ground, since a transistor 2 is an ON state and a transistor 3 is an OFF state, a DC type route does not exist, and a current is not caused to flow. Further, when the fuse is not disconnected, after a while after the power source is impressed, since transistors 6 and 8 are the OFF state though a transistor 5 is the ON state, or, the transistor 2 is the OFF state though the transistor 3 is the ON state, neither of them has the DC type route, and the current consumption does not occur.

JPH08274266	FUSE TRIMMING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT EQUIPPED THEREWITH
JP2010262711	SEMICONDUCTOR DEVICE HAVING ELECTRIC FUSE MEMORY
WO/2011/125455	OXIDE SEMICONDUCTOR MEMORY DEVICE

Torimaru Yasuo
Koji Hattori

JP30414587A

December 12, 1994

November 30, 1987

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KONINKLIJKE PHILIPS N.V.

G11C17/14; G11C17/06; H03K19/094; H03K19/0948; H03K19/173; (IPC1-7): G11C17/14

Takeshi Sugiyama (1 outside)

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