Title:
【発明の名称】周波数カウンタ及びデュティ・サイクル変調の影響を最小にするために信号の周波数を計数する方法
Document Type and Number:
Japanese Patent JPH06501554
Kind Code:
A
Abstract:
A dual-edge frequency counter and method for minimizing the effects of duty cycle modulation. In its simplest form, a dual-edge counter (50) includes a first counter (52) that accumulates reference clock pulses between successive rising edges of an input signal. An input signal is also applied to an inverter (54), which inverts the square wave signal prior to applying it to a second counter (56) that also accumulates reference clock cycles between successive rising edges of the inverted sensor signal. A summation junction (60) totals the accumulated counts from the first and second counters so that they can be averaged by a divider (62), which divides the total count by two. The technique is also employed in connection with a frequency counter that includes an integer counter (72) for totaling the number of cycles of the sensor signal occurring during a sample time defined by successive gate signals. The integer count, N, is then corrected for the compensated average of partial periods of the signal occurring at the beginning and the end of the sample time. The compensated average partial period corrects for variations in the sensor signal duty cycle caused either by noise superimposed on a sinusoidal signal produced by a quartz crystal (12) or as a result of variations in power supply level for the crystal oscillator.
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Inventors:
Halsing, Land H. The Second
Application Number:
JP51615891A
Publication Date:
February 17, 1994
Filing Date:
September 04, 1991
Export Citation:
Assignee:
Sandstrand Corporation
International Classes:
G01R23/10; G01P3/489; (IPC1-7): G01R23/10; G01P3/489
Attorney, Agent or Firm:
Soga Doteru (6 people outside)