Title:
【発明の名称】差動型ドライバ/レシーバ回路
Document Type and Number:
Japanese Patent JPH06506336
Kind Code:
A
Abstract:
A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal. The receiver circuit, during normal receiving operations, generates true and complement signals in response to the differential receive signal pair. During a test mode, the receiver circuit, in separate steps, compares the voltage levels of the true and complement receive signals to threshold voltages and generates an error signal if the selected true or complement receive signal does not have the proper relationship to the voltage level of the threshold voltage.
Inventors:
Wade, John, Pea.
Wells, David, Es.
Wells, David, Es.
Application Number:
JP50998692A
Publication Date:
July 14, 1994
Filing Date:
March 27, 1992
Export Citation:
Assignee:
Thinking Machines Corporation
International Classes:
H03K3/356; H03K5/02; H03K17/16; H03K17/687; H03K17/693; H03K19/003; H04B3/50; H04L25/02; H04L25/03; (IPC1-7): H03K17/687; H03K17/16; H03K19/003; H04B3/50
Attorney, Agent or Firm:
Yoshikazu Tani