Title:
【発明の名称】大量並列プロセッサ間の、階層的プロセッサ相互間通信ネットワークのための手順決定技術
Document Type and Number:
Japanese Patent JPH06507744
Kind Code:
A
Abstract:
A routing process for a single-instruction-multiple-data (SIMD) multi-level hierarchical network of nodes, which are arranged in clusters and interconnected by dual, unidirectional channels, are used to send data packets including routing address information during a succession of routing cycles from transmitting ones to receiving ones of a large number of parallel processors (e.g., 4096 processors arranged in a hierarchy of 8 cabinets, each of which contains a cluster of 8 circuit boards, with each circuit board containing a cluster of 64 processors). Each of the nodes includes a storage buffer having a capacity equal to a given number which is one more than the total number of channels terminating at that node. This routing process guarantees prevention of deadlock between levels and buffer overflow, and offers high-speed, low-cost interprocessor communication for SIMD computers.
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Inventors:
Lee, Sue-Kyong
Chin, Danny
Chin, Danny
Application Number:
JP51181892A
Publication Date:
September 01, 1994
Filing Date:
April 09, 1992
Export Citation:
Assignee:
Divided Than Off Research Center, Incorporated
International Classes:
G06F15/16; G06F15/173; G06F15/80; (IPC1-7): G06F15/80; G06F15/16
Attorney, Agent or Firm:
Yoshiki Hasegawa (5 others)