Title:
【発明の名称】多重プロセッサアレイ
Document Type and Number:
Japanese Patent JPH06508707
Kind Code:
A
Abstract:
A multiprocessor computer system wherein a base processor is coupled in asynchronous O-ring fashion to an associated input/output adapter, with the processor and I/O adapter each including associated private cache memory through which they are both connected with a common shared MP bus via a single connector channel.
Inventors:
Ho, Kin M
Carpaneck, Dietmar M
Lee, Adam W. Kay
Ryu, Jonathan W
Brian Jay, Sassoni
Seek, taheel cue
Tame, Sam
Carpaneck, Dietmar M
Lee, Adam W. Kay
Ryu, Jonathan W
Brian Jay, Sassoni
Seek, taheel cue
Tame, Sam
Application Number:
JP50154393A
Publication Date:
September 29, 1994
Filing Date:
June 19, 1992
Export Citation:
Assignee:
Unisys Corporation
International Classes:
G06F13/36; G06F13/12; G06F15/16; G06F15/173; G06F12/08; G06F12/0875; (IPC1-7): G06F15/16; G06F13/36
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)