Title:
【発明の名称】エミツタ結合論理回路
Document Type and Number:
Japanese Patent JPH0769398
Kind Code:
B2
Abstract:
An ECL logic circuit uses a single resistor (R5) in place of separate current-source and emitter-follower resistors. A single tap connects a point (205) on this resistor to the ground bus, and the signal--output line (131) connects to this resistor by a contact which is separate from the contact (231) connecting the emitter of the output transistor (T4) to the resistor.
Inventors:
Delbert Raymond Chieki
Ugui Vuang Huaan
Ugui Vuang Huaan
Application Number:
JP21214089A
Publication Date:
July 31, 1995
Filing Date:
August 19, 1989
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G01R31/30; H03K19/00; H03K19/086; G01R31/317; (IPC1-7): G01R31/317; H03K19/00; H03K19/086
Domestic Patent References:
| JP62146014A | ||||
| JP63152221A | ||||
| JP63273346A | ||||
| JP57107637A |
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)
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