【発明の名称】コンピュータ・メモリ・システム

Japanese Patent JPH0769864

B2

An electronic computer memory system has first and second intermediate memory levels for use between a central processing unit and a main memory level. One or more buffer arrays have two sets of bus lines. A first set of buffer array bus lines communicates with associated bus lines of the first and second intermediate memory arrays. The second set of buffer array bus lines contains a number of bus lines less than the number of bus lines in the first memory array. By providing one or more buffers with two sets of bus lines, data can be transferred between the main memory level and the buffer or one intermediate memory level while data in the other intermediate memory level is operated on by a the central processing unit. By providing the buffer with one set of bus lines equal to the number of bus lines of the first and second intermediate memory arrays, high speed data transfer between the intermediate memory arrays can be achieved.

JPH0573399	MEMORY SHARING METHOD BETWEEN WORK STATIONS
JP2000047936	MEMORY PACKAGING METHOD IN COMPUTER SYSTEM
JPH0385658	DATA PROCESSOR

Richard E. Matec
Stanley Everett Schuster

JP33013692A

July 31, 1995

December 10, 1992

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International Business Machines Corporation

G06F12/06; G06F12/00; G06F12/08; G11C7/10; G11C11/401; G11C11/413; (IPC1-7): G06F12/08

Koichi Tonmiya (3 outside)

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