Title:
【発明の名称】コンピュータ・メモリ・アレイ・コントロール
Document Type and Number:
Japanese Patent JPH08501643
Kind Code:
A
Abstract:
A computer memory controller for interfacing to a host computer comprises a buffer memory (26) for interfacing to a plurality of memory units (42) and for holding data read thereto and therefrom. A central controller (22) operative to control the transfer of data to and from the host computer and the memory units (42). The buffer memory (26) is controlled to form a plurality of buffer segments for addressably storing data read from or written to the memory units (42). The central controller (22) is operative to allocate a buffer segment for a read or write request from the host computer, of a size sufficient for the data. The central controller (22) is also operative in response to data requests from the host computer to control the memory units (42) to seek data stored in different memory units (42) simultaneously.
Inventors:
Hill, Andrew James William
Application Number:
JP51198493A
Publication Date:
February 20, 1996
Filing Date:
December 10, 1992
Export Citation:
Assignee:
Array Data Limited
International Classes:
G06F12/16; G06F3/06; G06F11/10; G06F12/08; G06F12/0866; G11B20/10; G11B20/18; (IPC1-7): G06F3/06; G06F12/16
Attorney, Agent or Firm:
Minoru Yoshida (2 outside)