Title:
【発明の名称】スーパースカラプロセッサにおけるトラップを検出して実行する装置
Document Type and Number:
Japanese Patent JPH10506739
Kind Code:
A
Abstract:
Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache or from main memory, an instruction FIFO memory for storing fetched instructions from the fetch stage, and an instruction decode stage for removing instructions from the FIFO memory in accordance with relative ages of instructions stored in the FIFO memory. The decode stage examines instructions removed from the FIFO memory for trapping conditions, and flushes all younger instructions from the FIFO memory in response to identification of a trap in an instruction. The decode stage distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage immediately causes the fetch address to be changed to the appropriate trap handler address.
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Inventors:
Ethereman David El
Application Number:
JP53252996A
Publication Date:
June 30, 1998
Filing Date:
April 02, 1996
Export Citation:
Assignee:
Hyundai Electronics America Inc.
International Classes:
G06F9/38; (IPC1-7): G06F9/38; G06F9/38
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)