Title:
【発明の名称】プログラ?ブル制御パラメー?を有するメモリ・システ?
Document Type and Number:
Japanese Patent JPH10510657
Kind Code:
A
Abstract:
A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation. Once the memory has been fabricated and characterized, the control parameters can be selected for optimum memory performance and loaded into the data storage units.
Inventors:
Looper Bar, Fran F.
Learn, Rel Dee
Chevalier, ?Ristoff Jay
Brinner, Iker S
Learn, Rel Dee
Chevalier, ?Ristoff Jay
Brinner, Iker S
Application Number:
JP50762297A
Publication Date:
October 13, 1998
Filing Date:
July 17, 1996
Export Citation:
Assignee:
Iron Ron Debye Inco Rated
International Classes:
G11C16/02; G11C5/00; G11C11/407; G11C16/06; (IPC1-7): G11C16/02; G11C16/02
Attorney, Agent or Firm:
Kunihiko Ohashi
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