Document Type and Number:
Japanese Patent JPS4848881
Kind Code:
A
Abstract:
1370104 Process control system LUCAS ELECTRICAL CO Ltd 14 Jan 1972 [15 Oct 1971] 48025/71 Heading G4H A system for controlling a process provides an output pulse of a duration determined by signals from two transducers representing parameters significant in the progress of the process. As shown, two transducers 22, 23 provide A.C. signals of a frequency indicative of the values of the parameters monitored, which signals are passed, via gates 71, 72 opened for a particular duration by a monostable 24, to counters 73, 75 and 74, 114 so that the value held therein at the end of the open interval of the gates is indicative of the values of the parameters. These values are passed to respective decoding circuits 13, 14 providing outputs to a diode matrix 77, i.e. the circuit 13 causes one of twelve input lines 11a-11p to be energized and the circuit 14 one of twelve sets 15a-15p of seven input lines to be energized. The matrix is arranged as shown where each dot represents a diode connection between two crossing wires. A seven-bit word indicative of both parameter values may thus be derived (e.g. if line 11a and unit 15a were to be activated the word 1001000 would be produced) and passed to a comparator 53. The start of an output pulse is indicated by the setting of a flip-flop 46 by a trigger device 45. This enables gate 47 to pass pulses from an oscillator 48 to a counter 49 which after having reached a predetermined value closes the gate 47 and opens the gate 51 to pass pulses to a counter 52 which counter provides the other input to the comparator 53. When the inputs to the latter become equal an output pulse is produced which is passed to a counter 54 and also as a reset signal to counters 73, 75, 74, 114 and a triggering signal to the monostable 25. This process is repeated 16 times when an output pulse is produced by counter 54 to reset flip-flop 46 and terminate the pulse. Thus the duration of the output pulse is proportional to the mean value of the parameters during the output period. The counter 49 and gate 47 act as a fixed delay device to increase the resolution of the output pulse at very small values thereof. Two further counters 86, 87 receive the output pulses from the comparator and add a corresponding count to the other counters prior to the input to the decoder to improve resolution of the inputs thereof. The frequency of the oscillator 48 may be varied by means 35 in accordance with variations in the value of at least one further parameter.
Application Number:
JP1291872A
Publication Date:
July 10, 1973
Filing Date:
February 07, 1972
Export Citation:
International Classes:
F02D41/34; F02D41/24; F02P5/15; G05B11/26; G05B11/28; G05B15/02; G05B19/08; F02M51/00; F02P9/00; (IPC1-7): F02P9/00