Document Type and Number:
Japanese Patent JPS4871154
Kind Code:
A
Abstract:
A digital processing system wherein a binary-coded decimal full adder forms along with a display shift register a loop-like circuit for circulating information signals. The system provides a series synchronism system which reduces the number of circuit elements.
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Application Number:
JP10457971A
Publication Date:
September 26, 1973
Filing Date:
December 24, 1971
Export Citation:
International Classes:
G06F7/494; G06F7/00; G06F7/508; G06F7/52; G06F15/02; (IPC1-7): G06F7/52