Document Type and Number:
Japanese Patent JPS4987270
Kind Code:
A
Abstract:
An improved integrated counter stage employing non-volatile MNOS memory elements in series with static load transistors to facilitate a non-complementing counter. Incorporated into the counter are means for reducing memory pulse feedthrough and for providing transient clipping, resulting in increased reliability.
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Application Number:
JP9135673A
Publication Date:
August 21, 1974
Filing Date:
August 16, 1973
Export Citation:
International Classes:
H03K21/00; H01L29/792; H03K21/40; (IPC1-7): G11C11/40