- Patent JPS513164

Document Type and Number:

Japanese Patent JPS513164

Kind Code:

A

Abstract:

A binary frequency-divider stage for an electronic wristwatch comprises a set of insulated-gate field-effect transistors (IGFETs) of one and the same conductivity type, one (T1) of these IGFETs and an associated series capacitor (C1) forming an amplifier located between one bus bar (M) of a d-c supply and a first one (11) of two a-c control leads carrying a pair of bipolar pulse trains ( PHI 1, PHI 2) of opposite phase. An incoming pulse sequence (VE1), of a cadence to be halved, is in phase with the pulse train ( PHI 2) on the other control lead (12) and may be derived directly therefrom (FIG. 5). The gate capacitance of the first IGFET (T1) can be charged in two steps by a first charging circuit including two IGFETs (T2, T3) which are alternately turned on by respective control pulses ( PHI 1, PHI 2) applied to their gates. A normally blocked discharging circuit, including two other IGFETs (T4, T5), serves to discharge that gate capacitance, the gate capacitance of one of the IGFETs (T5) of this discharging circuit being chargeable through a second charging circuit including two further IGFETs (T6, T7). The fifth IGFET (T5) is rendered conductive upon the successive occurrence of an incoming pulse (VE1) and a first control pulse ( PHI 1) respectively turning on the sixth and seventh IGFETs (T6, T7). Upon the conduction of the fourth IGFET (T4), in response to the next incoming pulse, the first IGFET (T1) is cut off whereby the next-following first control pulse ( PHI 1) gives rise to an outgoing pulse (VE2) on the junction (d) between that transistor and its series capacitor (C1). The gate of the fifth IGFET (T5) is discharged through an eighth IGFET (T8) controlled by the outgoing pulse. The third IGFET (T3) may be included in the normally blocked discharging circuit for the gate of the first IGFET (T1); alternatively, to prevent a premature discharge of that gate, the common terminal of the fourth and fifth IGFETs (T4, T5) may be recharged, after each incoming pulse (VE1) discharging this common terminal, by a ninth IGFET (T9) responsive to the first control pulse ( PHI 1).