Document Type and Number:
Japanese Patent JPS5249288
Kind Code:
B1
Abstract:
A concurrent entry preventing system for use in electronic calculating machines capable of preventing the erroneous arithmetic operation performed by the calculating machine. To this end, means is provided for yielding a warning signal indicative of the fact that two or more character keys are concurrently operated in a wrong course. This warning signal comprises the logical product of a signal indicative of operation of one of such characters by a signal indicative of operation of one or more of the remaining character keys, if the both character keys are concurrently operated.
Application Number:
JP2030270A
Publication Date:
December 16, 1977
Filing Date:
March 10, 1970
Export Citation:
International Classes:
G06F3/02; G06F11/08; G06F15/02; H03M11/22; (IPC1-7): G06F3/02; G06F15/02