Document Type and Number:
Japanese Patent JPS5325775
Kind Code:
B2
Abstract:
A unique control circuit that maintains the addressability to an invalidated page frame until execution is completed for all current instructions in all CPUs of a multiprocessing system which uses demand-paging and virtual addressing.
Application Number:
JP14414074A
Publication Date:
July 28, 1978
Filing Date:
December 17, 1974
Export Citation:
International Classes:
G06F12/00; G06F12/10; G06F12/14