Document Type and Number:
Japanese Patent JPS5344084
Kind Code:
B2
Abstract:
A method and circuit for deriving timing signals from received data through the detection of a predetermined digital code in the received data, the modification of the synchronization response rate in response to the detected code and the instantaneous control of timing signal phase in response to the detected code and its complement. A locally generated clock signal is rapidly synchronized at a first response rate until the code is detected. Thereafter, the clock signal synchronization is maintained at a second response rate lower than the first rate to provide a high degree of stability. A means is provided to retain clock signal synchronization during received outages.
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Application Number:
JP9773072A
Publication Date:
November 25, 1978
Filing Date:
September 30, 1972
Export Citation:
International Classes:
H04M11/06; H03K5/00; H04L7/00; H04L7/04; H04L7/08; H04L7/10; H04M3/42; H04M11/00; H04Q1/30; H04W88/02; H04W88/18; H04L7/033; (IPC1-7): H04Q1/44; H03K3/72; H04B7/26; H04L7/10