Document Type and Number:
Japanese Patent JPS5416385
Kind Code:
B2
Abstract:
A high speed counter capable of operating in the gigahertz range including a plurality of interconnected latch stages. Information or data is stored in a bipolar directly cross-coupled emitter-coupled cell. Data is selectively written into the cell and transferred between stages by means of a pair of emitter-coupled input or data switching transistors connected to each side of the cell in conjunction with a pair of emitter enable or clock responsive switching transistors selectively controlling current conduction through the cross-coupled cell and the pair of input or data switching transistors. The load circuit for each of the latch stages comprises cascode active circuit means for isolating the feedback lines or internal output nodes associated with the cross-coupled cell and the external data latch output terminals. Predetermined latch stages further include a switchable reset transistor connected to the active cascode load circuit means capable of selectively setting or resetting the counter.
Application Number:
JP4539975A
Publication Date:
June 21, 1979
Filing Date:
April 16, 1975
Export Citation:
International Classes:
H03K3/286; H03K3/012; H03K3/037; H03K3/289; H03K23/50; H03K23/54