Document Type and Number:
Japanese Patent JPS5441450
Kind Code:
B2
Abstract:
An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.
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Application Number:
JP13829575A
Publication Date:
December 08, 1979
Filing Date:
November 19, 1975
Export Citation:
International Classes:
G11C29/00; G01R31/3185; G06F11/22; G11C29/02; G11C29/12; G11C29/20