Document Type and Number:
Japanese Patent JPS566735
Kind Code:
B2
Abstract:
An FET load gate compensator circuit is disclosed which compensates for variations in the parameters characterizing the silicon substrate in FET large scale integrated circuit device, by generating a compensatory load gate voltage to be applied to the load gates of the functional circuits therein.
Application Number:
JP9882576A
Publication Date:
February 13, 1981
Filing Date:
August 20, 1976
Export Citation:
International Classes:
H01L21/8236; H03F1/30; H01L27/088; H03K3/011; H03K17/14; H03K17/687; H03K19/0944; H03L1/00
Next Patent: DRIVEN METHOD FOR ACTIVE MATRIX DEVICE