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Title:
SEMICONDUCTOR MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPS58128761
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for a resistor requiring large resistace value, and to contract the area of a memory cell by compositely forming three transistors constituting the memory cell into one isolated island.

CONSTITUTION: 11, 12 Indicate a pair of word lines and 13, 14 a pair of figure lines, and a PNP transistor TR15 and NPN TRs 17, 19 and a PNP TR16 and NPN TRs 18, 20 each indicate equivalently one PNPN type semiconductor elements 51, 52. One memory cell is constituted by these elements 51, 52. For select one memory cell from m×n memory cell groups formed in this manner, the potential of word lines 11, 12 to which the memory cell is connected is elevated selectively more than the potential of other word lines, and the switches 27, 28 of the figure lines 13, 14 to which the memory cell is connected are made selectively. According to such constitution, three TRs can be formed compositely into one isolated island, and a resistor need not be formed, thus contracting the area of the memory cell.


Inventors:
INABE YASUNOBU
KAWARADA KUNIYASU
Application Number:
JP1065682A
Publication Date:
August 01, 1983
Filing Date:
January 26, 1982
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G11C11/411; H01L21/8229; H01L27/102; (IPC1-7): G11C11/40; H01L27/10
Attorney, Agent or Firm:
Kugoro Tamamushi



 
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