PURPOSE: To obtain a decoder device superior in reliability, by comparing a signal, which indicates the odd or even parity, with output signals of the first and the second circuits which have true values only for the odd parity and the even parity of an input signal group respectively.

CONSTITUTION: A decoder circuit 16 decodes an input signal group given to input signal lines 11W1i to give true values only to a specific number of signal lines out of output signal lines 21W2n. Odd-numbered and even-numbered signal lines of signal lines 21W2n are inputted to OR circuits 18 and 19, respectively, and OR signals 12 and 13 which have true values only for the odd parity and the even parity respectively are outputted and are inputted to exclusive OR circuits 20 and 21, respectively. An odd/even discriminating circuit 17 connected to signal lines 11W1i discriminates the odd or even parity of the input signal group and gives the true value to a signal 10 or 11 in accordance with the odd or even parity and inputs signals 10 and 11 to the other iputs of circuits 20 and 21, respectively. When the circuit 16 is operated normally, signals 10 and 12 have true values and signals 11 and 13 have false values when the signal group having the odd parity is inputted, and output signals 14 and 15 of circuits 20 and 21 have false values together at this time; and thus, signals 14 and 15 are monitored to discriminate the operation of the circuit 16.