Title:
CONSTITUTION OF CHIP IN SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPS58161339
Kind Code:
A
Abstract:
PURPOSE:To calibrate the relationship between surface potential and secondary electron signal quantity accurately by forming at least one chip of the wafer by a conductive layer and using the chip as a chip for calibration. CONSTITUTION:When ICs are formed in a wafer 1 as a large number of chips 2, the chips 3 for calibration are formed in dispersed shape. Voltage such as +5V and 0V are changed over and applied in succession to the Al layers 4 of the chips 3 for calibration as reference voltage prior to the measurement of the wafer, electron beams are accelerated and focussed and irradiated under the state, secondary electrons discharged when the beams are projected to the layers 4 are collected by a collector electrode, and the secondary electron signal quantities are measured. The secondary electron signal quantities of the chips 3 for the calibration are used as reference, electron beams are irradiated and scanned to sections to which LSIs are formed, and the secondary electron quantities at each position are measured as voltage by a measuring circuit connected to a collector.
More Like This:
| JPS5965443 | SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP2002222840 | ELECTRONIC BEAM TESTER |
| JP2001093946 | ELECTRON BEAM TESTER, TESTING METHOD, ELECTRON BEAM DEVICE AND OBSERVING METHOD |
Inventors:
MIYOSHI MOTOSUKE
Application Number:
JP4409682A
Publication Date:
September 24, 1983
Filing Date:
March 19, 1982
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G01R31/302; H01L21/02; H01L21/66; (IPC1-7): H01L21/02
Attorney, Agent or Firm:
Takehiko Suzue