PURPOSE: To reduce the cost of chip on the basis of decreases in delay time, in output impedance and in the number of elements, by arranging four transfer switches in a bridge shape.

CONSTITUTION: Transfer switches 4, 5, 6 and 7 are connected as a bridge. The 1st exclusive OR input signal A and a complementary signal A' of the input signal A are added to terminals 1, 1' provided at a corner and its opposite corner of the bridge. An exclusive OR output Y and a complementary signal Y' of the output Y are extracted from terminals 3, 3' provided at the other conrer and its opposite corner. The 2nd exclusive OR input signal B is added to drive terminals of the transfer switches 5, 7 inserted in one side and its opposite side of the bridge from a terminal 2, and a complementary signal B' of the 2nd input signal B is added to driving terminals of the transfer switches 4, 6 inserted in the other side and its opposite side from a terminal 2'.