PURPOSE: To generate an automatic clearing signal stably even when electric power is supplied with a long time constant by connecting a resistace and a capacitor element in series across a power source and connecting an IG-FET to the capacitor element in parallel.

CONSTITUTION: An N type IG-FETN1 as the resistance element and the capacitor C are connected in series between the power source -VDD and ground, and a P type IG-FETP1 is connected to the capacitor C in parallel; and its drain is connected to a node A and the source and gate are grounded. Inverters I1 and I2 are connected to the node A in series to constitute a set signal generating circuit 1'. The output of the circuit 1' is supplied to an FF circuit 2, which generates the automatic clearing signal. The terminal voltage of the capacitor C drops to zero through the operation of the tailing area immediately after the power source has been turned on, so even when the electric power is supplied with the long time constant, the set signal is generated by the circuit 1' and the automatic clear signal is generated stably by the circuit 2.