PURPOSE: To reduce the access time without complicated manufacture process, by boosting a word line at a voltage higher than the power supply voltage for a memory cell at the selection of the word line and the power supply voltage for a peripheral circuit other than the cell.

CONSTITUTION: When a control input VC is VDD initially and changes to a VSS, the voltage VS is boosted to 2 VDD at a boosting circuit 21. Further, an input voltage Vin is VDD initially and a word line 10 is VSS at a word line drive circuit 20. When the word line 10 is selected, the voltage Vin is VSS after the potential of the control input VC changes from VDD to VSS, the voltage VS is impressed to the word line 10 via a drive FETP6 and the line 10 is boosted. Thus, at the selection of the line 10, the leading speed of the voltage of the line 10 is quickened by boosting the line 10 at a voltage 2VDD higher than the VDD for a memory cell 11 and the VDD for the peripheral circuit other than the cell, and the effective driving ability of the bit line is improved.