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Title:
SIGNAL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5824257
Kind Code:
A
Abstract:

PURPOSE: To improve the discrimination performance of the signal detecting circuit of an optical communication system receiver, by calculating and discriminating the optimum threshold value for every symbol when noise power has intercode interference.

CONSTITUTION: An arithmetic device 306 calculates a threshold value by two integrator outputs which correspond to the address signal from a shift register 302 and an address signal obtained by inverting one predetermined bit in the address signal. The calculated threshold value is applied from an integrator group 305 to the 2nd discriminator 307 which discriminates the signal obtained by delaying a demodulated signal from an input terminal 103, thereby discriminating and outputting a received signal finally. The threshold value is calculated as the best value for every symbol by using nise power with intercode interference, and the optimum discrimination result is obtained for a system having intercode interference.


Inventors:
MURAKAMI SHIYUUJI
Application Number:
JP12337981A
Publication Date:
February 14, 1983
Filing Date:
August 05, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H04B10/556; H03M5/04; H04B10/00; H04B10/07; H04B10/2507; H04B10/524; H04L25/06; H04L25/08; (IPC1-7): H04B9/00; H04L25/40
Attorney, Agent or Firm:
Kusano Takashi



 
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