PURPOSE: To strongly prevent destruction of information of a memory unit in an information processor, by enabling the processing to be continued normally when at least one information without any error exists in a plurality of memory units having the same real address.

CONSTITUTION: Readout of information from a plurality of memory units 1A, 1B, 1C having the same address is performed by setting a readout address stored in a register 16 to readout address registers 1, 2, 3 corresponding to the memory units 1A, 1B, 1C by one to one correspondingly at first. The information read out from the memory units 1A, 1B, 1C is stored in readout data registers 4, 5, 6 corresponding to each memory unit and the error detection is carried at error detection circuits 13, 14 and 15. If the readout information from the memory unit 1A has any error, an output signal of the circuit 13 goes to "1" and an output signal of the circuits 14 and 15 goes to "0", AND circuits 36 and 37 are energized and correct information is set to a register 17 via an OR circuit 39.