Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5844743
Kind Code:
A
Abstract:
PURPOSE:To improve the wiring efficiency of a semiconductor integrated circuit by gradually decreasing the thickness from the periphery of a cell array toward the center at the side contacted with the automatic wiring region between basic cells in the shape of power source wirings, thereby expanding the automatic wiring region. CONSTITUTION:Since a basic cell 1 is regularly disposed laterally and longitudinally in a gate array LSI, the power source of a power source wires 6-2... is large at the root 7 and is small at the center of the chip. Accordingly, the width of the wiring is as the conventional one at the root 7, and is narrowed at the center 8, thereby expanding (shaded part) the region between the cells. Or, the root 7 is widened as compared with the conventional one, and is narrowed gradually toward the center of the chip, thereby reducing the voltage drop at each art and supplying sufficient electric power to the center of the basic cell group. According to this structure, a gate array LSI having very good wiring efficiency can be obtained, thereby supplying sufficient power to the entire basic cell.
Inventors:
TANIZAWA SATORU
OOMICHI HITOSHI
MITONO KATSUHARU
OOMICHI HITOSHI
MITONO KATSUHARU
Application Number:
JP14294281A
Publication Date:
March 15, 1983
Filing Date:
September 10, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/822; H01L21/3205; H01L21/82; H01L23/52; H01L23/528; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Domestic Patent References:
| JPS5543840A | 1980-03-27 |
Attorney, Agent or Firm:
Yoshiyuki Osuge (1 outside)