Title:
【発明の名称】半導体基板の領域間に電気接触部を形成する方法
Document Type and Number:
Japanese Patent JPS58501485
Kind Code:
A
Abstract:
A process for making buried contacts without damaging the surface of the silicon substrate while etching the pattern of a poly interconnect layer. The contact cut made in the gate oxide layer covering the substrate is made smaller than the poly deposited and patterned thereover. Damage to the substrate surface during the etching of the poly layer pattern is prevented by the presence of the gate oxide layer between the poly layer and the substrate. An ion implantation step performed early in the process forms a parasitic depletion mode channel under the region having an overlap of poly onto gate oxide. Consequently, though the gate oxide prevents the direct diffusion of dopant into the underlying substrate when conductors are formed by doping, the parasitic channel ohmically couples the poly interconnect layer to the diffused region in the substrate. The latter region is usually the S/D electrode of an IGFET. The composite process is compatible with the formation of self-aligned gates and conductively doped poly and substrate regions which are simultaneously doped with the same impurity.
Inventors:
Onigfu Ord, Edward Herbert
Vynod Kumar, Darm
Vynod Kumar, Darm
Application Number:
JP50284882A
Publication Date:
September 01, 1983
Filing Date:
September 09, 1982
Export Citation:
Assignee:
NRC International Inc.
International Classes:
H01L21/28; H01L21/285; H01L21/336; H01L21/768; H01L21/3205; H01L29/78; (IPC1-7): H01L21/28; H01L21/88; H01L29/78
Domestic Patent References:
| JPS54128689A | 1979-10-05 |
Foreign References:
| US4052229A | 1977-10-04 | |||
| US4246044A | 1981-01-20 |
Attorney, Agent or Firm:
Yoshiaki Nishiyama