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Title:
MIS IC AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS5874083
Kind Code:
A
Abstract:

PURPOSE: To allow the multi-functions and high performance of an IC, by forming a second channel region in an epitaxially layer on one conductive type region formed by the same process as that of a first channel region.

CONSTITUTION: A P well 4 is formed on an N type Si substrate 10 by the implantation and diffusion of B. Next, an oxide film 5 on a region wherein an insulation gate static induction transistor (MOSSIT) is provided is opened, thus a non-single crystal Si thin film 24 is deposited, and accordingly the unnecessary part is removed. Thereafter, it is heat-treated in non-oxidizing atmosphere, the thin film 24 is formed into a single crystal layer 114 by a solid epitaxial growth, and thereat simultneously the crystal layer 114 is turned into P type with lower impurity density by the diffusion from the P well 4. Thereafter, N+ source and drain regions 11, 12 of an MOS transistor (MOST) T1, N+ source and drain regions 111, 112 of an MOSSIT T2 and respective gate oxide films 13, 113 are simultaneously formed, and then the MOST T1 is formed on the P well 4 and the MOSSIT T2 on the single crystal layer 114.


Inventors:
SHINPO MASAFUMI
Application Number:
JP17233481A
Publication Date:
May 04, 1983
Filing Date:
October 28, 1981
Export Citation:
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Assignee:
SEIKO INSTR & ELECTRONICS
International Classes:
H01L21/8234; H01L29/80; H01L27/06; H01L27/088; H01L27/092; H01L29/78; (IPC1-7): H01L29/78
Domestic Patent References:
JPS4931874A1974-03-22
JPS4911034A1974-01-31
JPS55162224A1980-12-17
JPS49130187A1974-12-13
JPS5491740A1979-07-20
Attorney, Agent or Firm:
Keinosuke Hayashi



 
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