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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5885561
Kind Code:
A
Abstract:

PURPOSE: To prevent the injection of carrier into a semiconductor substrate by forming an impurity implantation layer to be injected with the same conductive type impurity as the substrate on the substrate under a gate insulating film.

CONSTITUTION: A capacity between a gate electrode 3 and a p type semiconductor substrate 1 through a gate insulating film 2 forms a decoupling capacity. A p type impurity implantation layer 9 is formed by an ion implantation in a boundary between the substrate 1 and the film 2. A voltage higher than 10V is necessary to form a channel at this part due to a p type impurity implantation layer 9, and the channel is not formed at all with -3∼-4V of substrate bias voltage VBB to be applied between the electrode 3 and the substrate 1. Even if the voltage VBB is varied since the channel is not formed, electrons are not implanted into the substrate 1.


Inventors:
YAMADA MICHIHIRO
Application Number:
JP18395681A
Publication Date:
May 21, 1983
Filing Date:
November 16, 1981
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/04; H01L21/822; H01L27/10; H01L27/108; H01L29/78; (IPC1-7): G11C11/34; H01L27/10; H01L29/78
Domestic Patent References:
JPS5294783A1977-08-09
JPS5236478A1977-03-19
Attorney, Agent or Firm:
Masuo Oiwa