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Title:
GRAPHIC EQUALIZER
Document Type and Number:
Japanese Patent JPS59110215
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for a mixing circuit and a BPF for display and to display the signal intensity of each band securely by providing every amplification block with an amplifier which amplifies or attenuates only a band component set to each band-pass filter, and cascading those respective amplification blocks.

CONSTITUTION: Plural amplification blocks 26a∼26e are cascaded between a signal input terminal 27 and a signal output terminal 28 and provided with BPFs 9a∼9e and amplifiers 10a∼10e which amplify or attenuate only band components set by the BPFs 9a∼9e. Difference signals of subtracting circuits of those blocks 26a∼26e are applied to a multiplexer 32 to select and input band signals to a converting circuit 20 automatically and successively. Pieces of switching information on operation keys 16a and 16b are latched by latch circuits 14a∼14e through a shift register 30 and pieces of switching information C0∼C4 are applied to the blocks 26a∼26e and circuit 20 through a multiplexer 31. Thus, the need for a mixing circuit and a display BPF is eliminated and the signal intensity values of respective bands are displayed on display devices 8a∼ 8e by the output of the circuit 20.


Inventors:
NAKAYAMA YOSHIROU
NAGASAWA TAKAFUMI
Application Number:
JP22100882A
Publication Date:
June 26, 1984
Filing Date:
December 15, 1982
Export Citation:
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Assignee:
SANYO ELECTRIC CO
TOKYO SANYO ELECTRIC CO
International Classes:
H03G5/02; (IPC1-7): H03G5/00
Attorney, Agent or Firm:
Takuji Nishino



 
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