Title:
MULTIPLEX PROCESSOR SYSTEM
Document Type and Number:
Japanese Patent JPS6027063
Kind Code:
A
Abstract:
PURPOSE:To allot evenly the processes to plural processors only with addition of simple hardware by providing an exclusive logical circuit showing whether each processor is executing the data processing independently of a system control processor. CONSTITUTION:Each processor 12 has a shift of phase via a common bus 14 and gives an access to a shared memory 13 in time division. Then the execution of a program on the memory 13 is allotted to each processor 12. In this case, a control processor 10 gives an access to an allotment deciding circuit 19 which shows a state where a each processor 12 is used to other data processing. Thus the circuit 19 informs to the processor 10 the processor number to which the execution of processing requested from the processor 10. Based on this information, the processor 10 decides the allotted processor and gives a designation for data processing to the relevant processor 12.
Inventors:
MIYAYASU KENJI
KOSUGE YASUHARU
ISHIKAWA HIROSHI
KOSUGE YASUHARU
ISHIKAWA HIROSHI
Application Number:
JP13548083A
Publication Date:
February 12, 1985
Filing Date:
July 25, 1983
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04Q3/545; G06F15/16; G06F15/167; G06F15/177; (IPC1-7): G06F15/16
Domestic Patent References:
| JPS5199437A | 1976-09-02 |
Attorney, Agent or Firm:
Masatoshi Isomura