Document Type and Number:
Japanese Patent JPS6121011
Kind Code:
B2
Abstract:
A pulse generating device for speeding-up the rate of a pulse train from N to N+n wherein each of the pulses in the N+n pulse train is synchronized with the immediately preceding pulse in the original N pulse train. A count-up counter is reset upon each original pulse and counts up from zero, at frequency F/N+n, up to the following original pulse. A count-down counter is loaded with the contents of the count-up counter when the following original pulse occurs or when the output pulses occur with the exception of the last pulse in the interval when the time interval between said original pulses includes several generated output pulses, and is decremented at frequency F/M up to zero. A variable presettable counter provides the count-down counter with frequency F/M when each original pulse appears or when the output pulses appear with the exception of the last pulse in the interval when the time interval between the original pulses includes several output pulses. A control memory supplies values M to the variable counter in response to the original pulses or to the output pulses with the exception of the last pulse in the time interval between two original pulses. The output pulses are produced each time the count-down counter reaches value zero.
Inventors:
REMI UOOTEIE
Application Number:
JP10924579A
Publication Date:
May 24, 1986
Filing Date:
August 29, 1979
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
B41J2/51; B41B25/10; G06F7/68; G06K15/07; G06K15/08; G06K15/10; H03K3/72; H03K5/00