Document Type and Number:
Japanese Patent JPS6142451
Kind Code:
B2
Abstract:
A resonator circuit formed in MOS technology for scanned analog signals, wherein such circuits are constructed for use with accumulators and information processing is accomplished by means of switched capacitors which are charged or respectively connected to each other by way of clock pulse transistors. In the present invention, the realization of general ladder networks or branching circuits for builders in single layer MOS techniques is accomplished by utilizing a second continuous branch which is switched to a first accumulator stage by clock pulse switches and is connected with a reference potential through a capacitor as well as to a further accumulator input through a series switch. The signal series arms are connected with the outputs of the total accumulator arrangement by way of time delay transit elements. The total accumulator arrangement is expanded to a resonator of the type of a four pole network having two inputs to which one respective transmission and one respective reflection output is assigned by utilizing difference elements and transfer elements. The arrangement of the invention is suitable for use as general branching filter circuits, and an increase of the dynamic range by better suppression of the clock pulse pickup and the harmonic distortion of the second order occurs by utilizing push-pull arrangements.
Inventors:
HENMAN BETSUTSURU
ERUNSUTO HEEBENSHUTORAITO
ROORANDO SHURAIBAA
ERUNSUTO HEEBENSHUTORAITO
ROORANDO SHURAIBAA
Application Number:
JP8084379A
Publication Date:
September 20, 1986
Filing Date:
June 28, 1979
Export Citation:
Assignee:
SIEMENS AG
International Classes:
G06G7/161; G06G7/16; G06G7/22; H03H15/02; H03H17/00; H03H19/00