Document Type and Number:
Japanese Patent JPS6147075
Kind Code:
B2
Abstract:
The circuit provides damping for digitally controlled devices where the provision of power pulses in response to sensing a given device parameter may result in a regularity of pulses that causes a resonant condition with a frequency that interferes with other device functions or induces error conditions. The circuit shown randomizes to a motor by random gating of a sequence of commands retained in a shift register (31). Random gating from the shift register positions occurs through the use of a counter (33) driven by an oscillator, independent of other device functions and clocking circuits, in conjunction with an enabling circuit from a random digitized data source that enables or disables counter advance by the oscillator.
Inventors:
JON YAKOBU NIISUZU
Application Number:
JP5171883A
Publication Date:
October 17, 1986
Filing Date:
March 29, 1983
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G05D13/62; G05B21/02; H02P7/29; H02P29/00