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Document Type and Number:
Japanese Patent JPS6153799
Kind Code:
B2
Abstract:
An output circuit (OB) of a semiconductor device for suppressing erroneous operation due to potential variations of the power supply line or the ground line. The output circuit comprises an output stage inverter (T5, T6) connected between the power supply line (Vcc) and the ground line (Vss) and a clamping circuit (CL1, CL2, CL3) for clamping the voltages applied to the output stage inverter (T5, T6). An instantaneous large current which flows through the output stage inverter (T5, T6) during transition of its state is greatly suppressed so that erroneous operation is prevented.

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Inventors:
HIGUCHI MITSUO
YOSHIDA MASANOBU
Application Number:
JP10050981A
Publication Date:
November 19, 1986
Filing Date:
June 30, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C11/417; G11C7/10; H01L21/822; H01L27/04; H03K5/02; H03K17/04; H03K17/687; H03K19/003



 
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